General Info

Email: cxchen@fudan.edu.cn

Location: H2218 @ Fudan University, Handan Campus

(Online Teaching until on-campus teaching is allowed )

Time: Thursday Evening

Prerequisite: Verilog ( Digital Logic, and experiences by verilog/sv/chiesel/…)

[选修本课程的同学须有Verilog经验，熟悉《数字逻辑》的相关内容]

Score: Homework Assignement (15% x 4)+ Final Project/Presentation (40%)

Announcement

** Please ignore the unsafe notification and go the external video link.

Week	Date	wawswwaLecturewwwsawa	Slides	Video	HmWrk
1	3/5	Introduction (Overview, birth of microprocessors, and discovery of neural network )	Lec01	Part1 Part2 Part3
2	3/12	ISA (Dark Silicon, ISA and an ISA example for NN )	Lec02	Part1 Part2 Part3
3	3/19	Verilog and RISC hardware organization	Lec03	Part1 Part2	HW1 4/2 Due
4	3/26	Pipeline, Custom-Pipeline and super-scalar arch	Lec04	Part1 Part2 Part3
5	4/2	Vector/SIMD Architecture, and Quantization (i)	Lec05	Part1 Part2
6	4/9	No Class
7	4/16	Thread-level parallelism, and GPU	Lec06	Part1 Part2
8	4/24	RISC with instruction/data/thread-parallelism, and Systolic Array	Lec07	Part1 Part2	HW2 5/7 Due
9		No Class
10	5/14	Reconfigurable Architectures: CGRA & FPGA	Lec08	Part1 Part2
11	5/28	Review on Linear Classifier, Neural Network and CNN	Lec09	Part1 Part2	HW3 6/11 Due
12	6/25	Fast Winograd Convolution Algorithm, and data flow based architecture	Lec10	Part1 Part2
13		/
14		/
15		Final Project (No Class)	Proj
16		Final Presentation

The instructor thanks the contributors of the following materials